Advanced fine-grained cache power management
US9400544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2013 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.