Memory device and erasing method thereof
US9400712B2 · kind B2 · utility
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2References
20Claims
0Family size
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Key dates
| Filing date | Jan 22, 2014 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Sep 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasing method of a memory device is provided. The memory device includes a memory controller and a memory array having a first memory region and a second memory region. The first memory region and the second memory region share the same well. The erasing method comprising steps of: erasing the first memory region; and selectively programming the second memory region according to an error correction code algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.