Adaptive operation of 3D NAND memory
US9401216B1 · kind B1 · utility
4Cited by
39References
21Claims
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Key dates
| Filing date | Sep 22, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Sep 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.