MRAM initialization devices and methods
US9401226B1 · kind B1 · utility
4Cited by
6References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Sep 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a fail address region of the MRAM array, a first row of the fail address region including validity data, wherein the validity data includes multiple validity indicators, a last row indicator, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.