Semiconductor device
US9401319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Feb 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided, in which a first lead (11) is joined with the bottom electrode (23) of a MOS-FET (21) with first solder (51), the top electrode (22) of the MOS-FET is joined with an internal lead (31) with second solder (52), the internal lead is joined with a projection (61) of a second lead with third solder (53), and the first lead, second lead, MOS-FET and internal lead are integrally molded using sealing resin (41), wherein the first solder and second solder include support members (54) and (55), respectively, located thereinside and positions of the internal lead and MOS-FET are stabilized by self-alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.