Method of processing a semiconductor wafer

US9401343B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Achim Gratz · Dresden, DE
• Scott Wallace · Stillwater, US
• Tobias Jacobs · Mannheim, DE

Key dates

• Filing date: Feb 25, 2015
• Grant date: Jul 26, 2016
• Expiry date: Feb 25, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1306
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die.