E-flash cell band engineering for erasing speed enhancement
US9401434B2 · kind B2 · utility
2Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2014 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Sep 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/118
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.