Conditional pulse generator circuit for low power pulse triggered flip flop
US9401715B1 · kind B1 · utility
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2References
22Claims
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Key dates
| Filing date | May 21, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal. A pulse generation circuit is configured to compare the data input signal and an output signal at the output of the pulsed latch circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.