Reducing power consumption of uncore circuitry of a processor
US9405358B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 16, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.