Apparatus and method for non-blocking execution of static scheduled processor
US9405546B2 · kind B2 · utility
2Cited by
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16Claims
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Key dates
| Filing date | Mar 6, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Mar 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.