Patent · US Active

Synchronizing multiple threads efficiently

US9405595B2 · kind B2 · utility

1Cited by

36References

14Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sailesh Kottapalli · San Jose, US
John H. Crawford · Saratoga, US

Key dates

Filing date	Jul 24, 2014
Grant date	Aug 2, 2016
Priority date	—
Expiry date	Oct 7, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/084
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.