On-chip traffic prioritization in memory
US9405711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2013 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jun 10, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.