Semiconductor wafer and method of fabricating an IC die
US9406347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Dec 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules.There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.