Low latency, high bandwidth memory subsystem incorporating die-stacked DRAM
US9406361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jul 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem incorporating a die-stacked DRAM (DSDRAM) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (IC) package, a DSDRAM coupled to the processor, the DSDRAM implemented on the silicon interposer of the IC package, and a DRAM implemented separately from the IC package. The DSDRAM and the DRAM form a main memory having a contiguous address space comprising a range of physical addresses. The physical addresses of the DSDRAM occupy a first contiguous portion of the address space, while the DRAM occupies a second contiguous portion of the address space. Each physical address of the contiguous address space is augmented with a first bit that, when set, indicates that a page is stored in the DRAM and the DSDRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.