(110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate
US9406518B2 · kind B2 · utility
2Cited by
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18Claims
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Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jul 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.