Stack memory
US9406652B2 · kind B2 · utility
4Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | May 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory is formed by stacking a plurality of substrates and memory cells on each substrate are connected by data dump lines. A switch may intervene between the memory cell and the data dump line. When data of each substrate is dumped by the data dump line, a problem of decrease in a speed and an increase in power consumption due to a parasitic component can be minimized. Further, a core circuit including the memory cell may be disposed on one substrate and a peripheral circuit unit may be disposed on the remaining substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.