Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate
US9406679B2 · kind B2 · utility
10Cited by
8References
9Claims
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Key dates
| Filing date | Jul 26, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jul 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.