Balasubramanian S. Haran
84Patents
13h-index
39Co-inventors
76Inventor score
Filing activity: Oct 1, 2009 → May 16, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8569152B1 | Cut-very-last dual-epi flow | Electricity | 59 | Active |
| US8420459B1 | Bulk fin-field effect transistors with well defined isolation | Electricity | 57 | Active |
| US8358012B2 | Metal semiconductor alloy structure for low contact resistance | Electricity | 37 | Active |
| US8232607B2 | Borderless contact for replacement gate employing selective deposition | Electricity | 33 | Active |
| US8581320B1 | MOS capacitors with a finfet process | Electricity | 24 | Active |
| US8455932B2 | Local interconnect structure self-aligned to gate structure | Electricity | 24 | Active |
| US8999774B2 | Bulk fin-field effect transistors with well defined isolation | Electricity | 19 | Active |
| US8987790B2 | Fin isolation in multi-gate field effect transistors | Electricity | 19 | Active |
| US8309447B2 | Method for integrating multiple threshold voltage devices for CMOS | Electricity | 19 | Active |
| US8932918B2 | FinFET with self-aligned punchthrough stopper | Electricity | 18 | Active |
| US8604539B2 | Bulk fin-field effect transistors with well defined isolation | Electricity | 17 | Active |
| US8592290B1 | Cut-very-last dual-EPI flow | Electricity | 15 | Active |
| US8623712B2 | Bulk fin-field effect transistors with well defined isolation | Electricity | 15 | Active |
| US8377795B2 | Cut first methodology for double exposure double etch integration | Electricity | 11 | Active |
| US8383490B2 | Borderless contact for ultra-thin body devices | Electricity | 11 | Active |
| US8394710B2 | Semiconductor devices fabricated by doped material layer as dopant source | Electricity | 11 | Active |
| US8617961B1 | Post-gate isolation area formation for fin field effect transistor device | Electricity | 11 | Active |
| US9087741B2 | CMOS with dual raised source and drain for NMOS and PMOS | Electricity | 11 | Active |
| US8569125B2 | FinFET with improved gate planarity | Electricity | 11 | Active |
| US8946792B2 | Dummy fin formation by gas cluster ion beam | Electricity | 10 | Active |
| US9406679B2 | Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate | Electricity | 10 | Active |
| US9269629B2 | Dummy fin formation by gas cluster ion beam | Electricity | 10 | Active |
| US8928067B2 | Bulk fin-field effect transistors with well defined isolation | Electricity | 10 | Active |
| US9082873B2 | Method and structure for finFET with finely controlled device width | Electricity | 9 | Active |
| US8796128B2 | Dual metal fill and dual threshold voltage for replacement gate metal devices | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.