Flash memory unit and memory array, and programming, erasing and reading method thereof
US9406685B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Dec 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.