Component in the form of a wafer level package and method for manufacturing same
US9406747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jun 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06568
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.