Simple and cost-free MTP structure
US9406764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate prepared with an isolation well, a HV well region and first and second wells disposed in the substrate. The memory cell further includes a first transistor having a select gate and a second transistor having a floating gate adjacent to one another and disposed over the second well. The transistors include first and second diffusion regions disposed adjacent to the sides of the gates. A control gate is disposed over the first well and coupled to the floating gate. The control and floating gates include the same gate layer extending across the first and second wells. The control gate includes a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.