Semiconductor structure and manufacturing method thereof
US9406771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.