Programmable delay circuit
US9407247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Oct 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0015
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.