Fast locking clock and data recovery using only two samples per period
US9407424B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Apr 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.