Multistage low leakage address decoder using multiple power modes
US9411391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jun 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.