Global write driver for memory array structure
US9411392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Nov 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.