Method and apparatus for improving sequential memory read preformance
US9411521B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Aug 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present technology is directed to a method for accessing a memory device in response to read requests is described. The method comprises, in response to a first request, composing a first read sequence using a command protocol of the memory device. The first read sequence includes a command code and a starting physical address. Upon receipt of a second request, the method determines a starting physical address of a second read sequence according to the command protocol of the memory device. If the starting physical address of the second read sequence is sequential to an ending physical address of the first read sequence, then the method composes the second read sequence using the command protocol without a command code, else the method composes the second read sequence using the command protocol with a read command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.