Split write operation for resistive memory cache
US9411727B2 · kind B2 · utility
3Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.