Weak bit detection using on-die voltage modulation
US9412469B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Feb 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.