Multilayer ceramic capacitor with terminals formed by plating
US9412519B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2012 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method is provided for concurrently forming terminals on a multilayer capacitor having a first plurality of interior plates with edges that are brought to and exposed upon a first surface and a second plurality of interior plates, interleaved with the first plurality of interior plates, and spaced from the first plates by a dielectric. The second plurality of interior plates has edges that are brought to and exposed upon a second surface, which is not adjacent to the first surface. A first terminal is formed by plating a layer of electrically-conductive first metal directly onto the first surface including where the edges of the first plates are exposed upon the first surface and concurrently forming a second terminal by plating a layer of electrically-conductive first metal directly onto the second surface including where the edges of the second plates are exposed upon the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.