Through silicon via (TSV) process
US9412653B2 · kind B2 · utility
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11References
11Claims
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Key dates
| Filing date | Aug 4, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.