Semiconductor device having jumper pattern and blocking pattern
US9412693B2 · kind B2 · utility
3Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jul 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.