Semiconductor memory device and production method thereof

US9412754B1 · kind B1 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventor

• Toshihiko Iinuma · Yokohama, JP

Key dates

• Filing date: Sep 10, 2015
• Grant date: Aug 9, 2016
• Expiry date: Sep 10, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/62

Abstract

A semiconductor memory device includes a silicon substrate having an impurity diffusion region, and a memory cell array. The memory cell array includes conductive layers laminated on the silicon substrate via interlayer insulation layers, a semiconductor layer extending in a direction of the lamination of the conductive layers, a charge storage film disposed between the conductive layers and the semiconductor layer, and an electrode disposed on the conductive layers. A groove having a direction of the lamination as a depth direction and a first direction different from the lamination direction as a lengthwise direction is formed through the conductive layers. The silicon substrate includes a silicide film disposed in the impurity diffusion region along the groove. The memory cell array includes a conductor, which is in contact with the electrode and the silicide film, in the groove. In the first direction, the conductor is shorter in length than the groove.