Aligned gate-all-around structure
US9412828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region and a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion. A source and a drain region are disposed adjacent the gate. A dielectric layer is disposed on the substrate and has a first portion underlying at least some of the source, a second portion underlying at least some of the drain; and a third portion underlying at least some of the first channel, the first gate portion and the second gate portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.