Method for fabricating semiconductor device
US9412842B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Jul 3, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jul 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.