Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed edge
US9412851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Jan 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.