Graded vias for LED chip P- and N- contacts
US9412907B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Apr 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/816
Abstract
The present disclosure provides various embodiments of light emitting chips and packages with improved current spreading structures, such as non-uniform via structures or varied via structures. In some embodiments, these structures may be used to regulate current flow and current crowding in order to improve emitter efficiency and uniformity. Some embodiments of this disclosure may also refer to contact pad placement to improve current flow. In some embodiments of non-uniform via structures, the size of the vias may vary, whereas in other embodiments, the shape or spacing between the vias may vary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.