Systems and methods of phase frequency detection with clock edge overriding reset, extending detection range, improvement of cycle slipping and/or other features
US9413295B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Mar 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods associated with phase frequency detection are disclosed. In one illustrative implementation, a phase frequency detection (PFD) circuit device may comprise first circuitry and second circuitry having a set input, a reset input, and an output, wherein the set input has a higher priority than the reset input, and additional circuitry arranged and operatively coupled to provide advantageous operation of the PFD circuit device. According to some implementations, for example, systems and methods with clock edge overriding reset features, extended detection range(s), and/or reduction of reverse charge after cycle slipping are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.