Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS)
US9413378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2015 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Sep 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.