High throughput low-density parity-check (LDPC) decoder via rescheduling
US9413390B1 · kind B1 · utility
8Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Jul 16, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Nov 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A LDPC decoder utilizes a new schedule that breaks a dependency between data of different layers of a parity check matrix, so that the forward scan in the next layer can begin to perform after a predetermined time has elapsed (i.e. a delay) since the backwards scan of the previous layer has begun, and before the backwards scan of the previous layer is completed. Accordingly, the computation at the next layer can begin as soon as possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.