Instruction and logic to perform dynamic binary translation
US9417855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Sep 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/51
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.