Method for integrated circuit patterning
US9418862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3081
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.