Wrap around silicide for FinFETs
US9418897B1 · kind B1 · utility
207Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Jun 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.