Integrated circuits with selective gate electrode recess

US9418898B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Srijit Mukherjee · Hillsboro, US
• Christopher J. Wiegand · Portland, US
• Tyler J. Weeks · Hillsboro, US
• Mark Liu · West Linn, US
• Michael L. Hattendorf · Beaverton, US

Key dates

• Filing date: Nov 19, 2014
• Grant date: Aug 16, 2016
• Expiry date: Nov 19, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.