Three-dimensional semiconductor memory device having sidewall and interlayer molds
US9418911B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Oct 28, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Oct 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.