Package structure and manufacturing method thereof
US9418931B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 2015 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4644
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a package structure includes the following steps. A substrate including a core layer, first and second patterned metal layers is provided. The first and second patterned metal layers are respectively disposed on two opposite surfaces of the core layer. A through cavity penetrating the substrate is formed. The substrate is disposed on a tape carrier. A semiconductor component is disposed in the through cavity. An inner wall of the through cavity and a side surface of the semiconductor component define a groove. The filling compound is dispensed above the groove. A heating process is performed for the filling compound to flow toward the tape carrier and comprehensively fill the groove. First and second stacked layers are respectively laminated onto the first and second patterned metal layers and cover at least a part of the semiconductor component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.