Multi-layered integrated circuit with selective temperature coefficient of resistance
US9418982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second resistor having a second trench in the dielectric layer, the second trench having a second width not equal to the first width; a trench in a dielectric layer, a first conductive layer having a first TCR and coating at least a portion of the first trench and the second trench; and a second conductive layer having a second TCR and coating at least a portion of the first conductive layer in each of the first trench and the second trench, wherein the second TCR is not equal to the first TCR, and wherein the TCR of the IC is selected based on a dimension of the trench, a thickness of the first conductive layer, and a thickness of the second conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.