Chip scale package of image sensor having dam combination
US9419033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16235
Abstract
Disclosed is a chip scale package of image sensor having a dam combination, comprising an image sensor chip, a dam combination, a transparent lid disposed on the dam combination, and a plurality of external terminals disposed on the backside of the chip. An image sensing area is formed on the active surface of the image sensor chip. A dam combination consists essentially of at least two dam parts and has an image sensing window. The peripheries of the image sensor window are formed by a pre-formed dam part and are adjacent to the image sensing area with horizontal spacing not greater than 200 μm. There is a combination interface between the two dam parts. The combination interface and the post-formed dam part are far away from the image sensing area than the pre-formed dam part to keep residues caused by the disposition of the pre-formed dam part to be away from the 200 μm exclusive region around the image sensing area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.