Low power scheme to protect the low voltage capacitors in high voltage IO circuits
US9419613B2 · kind B2 · utility
2Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2014 |
| Grant date | Aug 16, 2016 |
| Priority date | — |
| Expiry date | Nov 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018592
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input/output (IO) circuit includes a first bias circuit and a second bias circuit coupled to a node. A first capacitor and a second capacitor are being cascaded and coupled to the node. The node is defined between the first capacitor and the second capacitor. A pad is coupled to the node. The first bias circuit maintains a voltage at the node below a threshold during a transmit mode and a receive mode of the IO circuit and the second bias circuit maintains the voltage at the node below the threshold during the receive mode. The voltage at the node is dependent on a voltage at the pad during the receive mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.