Method and apparatus for transitioning a system to an active disconnect state
US9423847B2 · kind B2 · utility
2Cited by
1References
25Claims
0Family size
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Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Aug 23, 2016 |
| Priority date | — |
| Expiry date | Dec 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.